1. Field of the Invention
The present invention relates to a semi-conductor integrated circuit and in particular to a semiconductor integrated circuit provided with a test circuit for testing an output buffer gate.
2. Description of the Prior Art
It is usual that a semiconductor integrated circuit, after manufacture, is subjected to DC, AC and function tests to ascertain the conformity of the circuit with DC and AC standards and also to check performance characteristics of the overall circuit. Of these tests a DC test is our present concern.
The DC test includes tests of an input buffer gate, an output buffer gate, and a bidirectional buffer gate (an input/output buffer gate). For brevity, a buffer gate will be referred to as a buffer below. Among these DC tests, the test of an input buffer can be easily performed by applying a test-data signal (a test pattern) fed from an external circuit directly to the input buffer to be tested. A test of an output buffer, however, is not so easy as that of the input buffer, because test-data signals have to be supplied from an internal circuit of the semiconductor integrated circuit, and it is usually difficult to apply test patterns to the internal circuit and control the internal circuit so as to allow the output buffer to provide an output of a predetermined state by means of an appropriate combination of a test-data signal and a control signal supplied from the internal circuit. (A typical test of a buffer is to measure a current and a voltage in the buffer to be tested at a time when the buffer provides an output of a predetermined state.) This difficulty increases as a circuitry of the internal circuit becomes more complicated. In order to avoid this difficulty, it has been proposed that the semiconductor integrated circuit internally have a test circuit capable of selecting one of two modes, a test mode and an output mode, in response to a mode-selecting signal or a test-mode signal supplied from an external circuit. In the test mode, an externally supplied test-data signal is fed to the output "buffer" to be tested, and in the output mode, a signal delivered from the internal circuit is transmitted to a given external circuit through the output buffer.
FIG. 1 shows a block diagram of a semiconductor integrated circuit provided with a conventional test circuit of the type described above, and FIG. 2 shows a block diagram of a multiplexer employed in the test circuit shown in FIG. 1.
A three-state buffer is inserted in the test circuit as output buffer 1 to be tested. The main part of the test circuit comprises two multiplexers 6A and 6B. Multiplexer 6A receives logic signal Q delivered from an internal logic circuit (not shown) at first data input D1 and a test-data signal (hereafter referred to as "TSTD") transmitted from an external circuit through TSTD terminal 3 and input buffer 8 at second data input D2, and selects one of the two data signals in response to the test-mode signal (hereafter referred to as"TST") applied to the control-input terminal A, to provide a data input to three-state output buffer 1. TST is supplied, from an external circuit through TST terminal 2 and input buffer 7. Similarly, multiplexer 6B is fed at data inputs D1, D2 with two control signals, i.e., control signal C supplied from the internal logic circuit and a test-control signal (hereafter referred to as "TSTC") supplied from an external circuit through TSTC terminal 4 and input buffer 9. These control signals act as an output-enable signal for the output buffer 1. Multiplexer 6B selects one of the two control signals in response to TST applied to control input terminal A to provide a control input of output buffer 1.
Both multiplexers 6A, 6B have an identical circuitry. Each multiplexer is composed of AND gates 61, 62, OR gate 63 and inverter 64 as shown in FIG. 2. Since TST and inverted TST are supplied to one of the inputs of each AND gate 61, 62, respectively, two AND gates 61, 62 work complementarily to each other in response to TST. As a result, when TST is at logic 1, AND gate 61 is allowed to transmit data input D1 which is subsequently delivered to output buffer 1 through OR gate 63, while AND gate 62 is inhibited from transmitting data input D2. Conversely, when TST is at logic 0, data input D2 is delivered to output buffer 1.
The construction of the test circuit above leads to the operation below. In the output mode, TST is set at logic 1, thus logic signal Q and control signal C are selected by multiplexer 6A and 6B, respectively, to be delivered as a data signal and a control signal, respectively, to three-state output buffer 1, whereby output buffer allows logic signal Q to transmit to the external circuit under control of control signal C, provided that output buffer 1 functions correctly, while TSTD is shut out from the output buffer. In the test mode, when TST is set at logic 0, it causes logic signal Q and control signal C to be shut out from output buffer 1, while TSTD and TSTC are allowed to transmit to output buffer 1, which allows TSTD to transmit to output terminal 5 under control of TSTC, provided that output buffer 1 functions correctly. Combining TSTD and TSTC appropriately, output terminal 5 can easily be set in any state of logic 1, logic 0 and high impedance.
Table 1 is a truth table of the logic state at output terminal 5 for various logic levels of signals Q, C, TST, TSTD, and TSTC. In the table, HZ and X stand for "high-impedance" and "irrelevant" (or "don't care") conditions. Since, by employing a test circuit as described above, output terminal 5 is easily set at any logic state optionally in accordance with the truth table, a test of DC characteristic of a three-state output buffer can be performed easily.
TABLE 1 ______________________________________ Terminal Q C TST TSTD TSTC 5 ______________________________________ 1 1 0 X X 1 0 1 0 X X 0 X 0 0 X X HZ X X 1 1 1 1 X X 1 0 1 0 X X 1 X 0 HZ ______________________________________
In the semiconductor integrated circuit with a conventional test circuit as set forth above, separation of transmissions of signal Q and TSTD is achieved by multiplexers 6A and 6B. This separation leads, however, to a problem in that in the output mode the multiplexer disposed on the transmission line of signal Q causes a delay in the transmission.